Porting MinSoc OpenRISC SoC to the Nexys2

I recently discovered the "MinSoc" project on OpenCores. Its boasts some really impressive features; A fully open source SoC with jtag hardware debugging, wishbone compliant bus, full simulation capabilities, full software toolchains, and a strong community behind it. The default distribution ships with support for a board very similar to mine, so how hard could it be?

Note: This all happened late December, and I am just now publishing it.

First I have to reiterate how excited I am about this project. Having hardware debugging tools that are usually available in professional kits is fantastic. I'm also looking forward to being able to reduce bring-up time on new cores buy putting them on the Wishbone bus.

Following the instructions per their website, I was able to check out and build all the tools they described.

I started off by attempting to simulate and synthesize the "spartan3e_starter_kit" included with the build. I figure my board is also based off the Spartan 3E-500, so its a logical starting place. This was extremely easy, and worked without any fuss. I was able to compile a simple C program and get it running with little effort.
One of my big complaints doing cross compilation is how horrendously bad toolchains can be to get running. This was a completely painless!

The next step I took was to build a board support package for the Nexys2. Their documentation was good, but I encountered some difficulties in simulation. It is my understanding that during simulating they use generic drop in replacements for chip specific features (Like a DCMs and BRAMs). Their documentation lacked the necessary information to properly describe how to remove chip specific features during simulation. Once I figured this out and fixed it, I updated their documentation.

Once I created and installed the board support package I didn't bother simulating, I jumped straight to synthesis. I clicked synthesize and a couple minutes later I get the following:

1 signals are not completely routed. See the minsoc_par.unroutes file for a list of all unrouted signals.

Aww, damn!


   Number of BSCANs                          1 out of 1     100%
   Number of BUFGMUXs                        3 out of 24     12%
   Number of DCMs                            1 out of 4      25%
   Number of MULT18X18SIOs                   4 out of 20     20%
   Number of RAMB16s                        18 out of 20     90%
   Number of Slices                       4656 out of 4656  100%
   Number of SLICEMs                        24 out of 2328    1%

Clearly the default MinSoc project is too big for the Nexys2, and too big for pretty much any 3E-500. Its failing by a single net. Arrrgh!

So, what next? I put a good bit of time into this, so I'm not giving up yet. There are some hints on their site to reduce usage, but it isn't explained what these features I'm blindly disabling do.

Here is the MinSoC board support package for the Nexys2 500 so far. This isn't fully functional yet; When I get some time I'll update it